This application claims the priority benefit of Taiwan application serial no. 88121169, filed Dec. 3, 1999.
1. Field of the Invention
The invention can be applied to a structure of a printed circuit board or a ball grid array (BGA) board to greatly reduce the mutual inductance among two adjacent transmission lines on a substrate.
2. Description of Related Art
Once PC/XT and later PC/AT personal computers were developed by IBM, many manufacturers have produced IBM PC-compatible personal computers to make this kind of personal computers be worldwide used.
Although, there is a great progress on hardware and software technologies, the layout of the main boards (generally called AT main boards) of the worldwide used personal computers still follow an original way. Furthermore, the areas of main boards are further reduced as BABY AT main boards due to the improvement of hardware, resulting in minimized personal computers. Today, the BABY AT is popularly used and therefore called AT thereinafter. Since personal computers are manufactured on complete production lines, the specification of main boards must meet a standard requirement so as to match with various PC cases or install different interface cards, for example: the specification of the areas of the main boards, the arrangement of interface slots or the positions of countersinks.
Although the specifications of the AT main board are always followed by manufacturers, it is not completely suitable for current personal computers because of the improvement of hardware and software. For example, a mouse has been a standard accessory for a personal computer, but it is necessary to additionally install a RS232 serial port to electrically connect the mouse, resulting in inconvenience. For such reason, another ATX specification which allows some common interfaces to be provided on a main board directly has been developed, wherein main boards with the ATX specification are called ATX main boards.
At present, devices on the main board of a personal computer at least includes a central processing unit (CPU). If the main board has a multi-processing function, it can include more than one CPU. In addition to CPU, the main board has an accelerated graphics part (AGP) connected to a display card, memory slots for the insertion of modular memories and peripheral component interconnects (PCI) for installation of various interface cards. Furthermore, anther control circuit is mostly designed in a chip set which must be connected to the CPU, memories, AGP slots and PCI slots. The arrangement of the pins of the chip set with respect to the positions of other devices must be taken into account. Especially, data processed by the CPU all are 32-bit or more than 32-bit data. Therefore, there are several hundreds of transmission lines among the chip set, CPU, memories, AGP slots and PCI slots. On the other hand, since the clock frequency of the CPU is as high as several hundred MHz, it should be careful during the circuit layout of the main board to ensure the main board stability.
A part of the prior art for a ball grid array (BGA) board or a printed circuit board layout is shown in FIG. 1. A chip set, such as Intel-made chip set 440BX, is mounted on the above conventional ball array board or the printed circuit board. Generally, the chip set has a square flat package with a thickness of several millimeters. Moreover, there are two square planes on both sides of the chip set, wherein one has electrical balls and the other is printed with a text label. In FIG. 1, transmission lines 11, 12, 13 are parallel to one another on a conventional printed circuit board. The mutual inductance of any two adjacent transmission lines has a logarithmic relation with spacing. Therefore, even though the spacing between two adjacent transmission lines is increased, the corresponding mutual inductance can not be effectively reduced. Furthermore, since the clock frequency of a currently used CPU is over several hundred MHz, the mutual inductance of the transmission lines 2 and 3 and transmission lines 2 and 1 becomes more serious. In turn, the mutual inductance then causes a cross-talk effect, resulting in a data error.
FIG. 1A shows a top view of FIG. 1, wherein reference symbols L1, Ls, L2 represent the self-inductance of transmission line 11, 12, 13, respectively, and reference symbol Lm represents the mutual inductance between the transmission line 12 and 13 or the one between transmission lines 12 and 11. Each transmission line has a width of 80xcexcm and a length of 10000 xcexcm, and the spacing between any two adjacent transmission lines is 70xcexcm.
FIG. 1B shows a cross-sectional view of FIG. 1A. In FIG. B, reference symbol h represents a spacing between the transmission lines 11, 12, 13 and a ground plane, wherein the distance h is 100xcexcm, the thickness d1 of each transmission line is 27 xcexcm and the thickness d2 of the ground plane is 35 xcexcm.
Next, Table 1 shows the values of the self-inductance and mutualxe2x80x94inductance of transmission lines of FIG. 1. The self-inductance and mutual inductance are obtained by using Ansoft-Spicelink simulation software under a circumstance of f=100 MHz.
As shown in Table 1, the conventional layout can not reduce the mutual inductance effectively between two adjacent transmission lines.
A simple formula for calculating the mutual inductance between any adjacent transmission lines is given by:
Lm/l =(xcexc/4Pi)ln(1+(2h/S)2) (xcexcH/m)
Wherein
l:the length of each transmission line
xcexc:permeability
Pi:3.14159
h:the distance between the transmission lines and ground layer
s:the pitch of two adjacent transmission lines
As stated in the above formula, the mutual inductance Lm has a logarithmic relation with respect to the space. That is why the mutual inductance Lm can not be effectively reduced just by increasing the spacing.
In summary, the layout of a conventional ball grid array board or printed circuit board has the following disadvantages: the mutual inductance between two adjacent transmission lines can not be effectively reduced. In particular, when the clock frequency of a CPU is as high as several hundred MHz, the mutual inductance between two adjacent transmission lines will become much more serious.
An object of the invention provides a structure for reducing the mutual inductance between two adjacent transmission lines. With such structure, even though the clock frequency of a used CPU is over hundred MHz, the mutual inductance and cross-talk induced by the mutual inductance can be effectively reduced. Under a circumstance with an equal pitch of transmission lines, the mutual inductance between two adjacent transmission lines can be reduced down to {fraction (1/4xcx9c16)} times than an original mutual inductance. Moreover, for a two-layer ball grid array board without the ground plane, the effect will become more obvious.
A structure for reducing the mutual inductance between two adjacent transmission lines on a substrate according to the invention can be applied on the layout of a main board. The structure includes a loop-shaped transmission line, at least one transmission line located on each side of the loop-shaped transmission line, wherein one end of the loop-shaped transmission line is linked to mother board and a diagonal end is connected to an signal input on the substrate. The loop-shaped transmission line has a short side with a length equal to xc2xd of the wavelength of an input signal.